On Thu, Aug 3, 2017 at 12:37 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Here we can see the effect of changing the single-ended impedance on width and spacing of traces in a differential pair of given differential impedance. By raising the single-ended impedance we reduced both the width of the traces and also the spacing.
i know from DDR3 that they can change (dynamically) the end-impedance both on the SoC and in the DDR3 RAM ICs. it means you can stick with a particular track width and spacing then have the SoC and DDR3 ICs adjust each end to suit.
Toradex mentions the lower impedance between wide traces and the reference plane causing impedance mismatch at large pads for components and connectors.[21]
yehyeh. fortunately the ones on the DC3 connector are tiny.
i think you're saying we're ok here with 5mil track, 5mil spacing, and lots and lots of ground vias. i can't get them in between the diff-pairs though.
l.