ralf, dominique, phil: i believe this is what i'm looking for, let me try and work through it, see if i got it right:
http://upload.wikimedia.org/wikipedia/commons/thumb/8/81/TTL_NOT_gate.svg/50...
except, the 1st transistor will be supplied by VREFTTL (from the CPU) and the 2nd is supplied by VCC-3V3 (from the STM32F).
the 1st transistor is against the flow of current in the instance where VREFTTL is less than VCC-3V3.
when the input is at 0V:
* 1st transistor goes "on", so current flows through the 1st resistor (at VREFTTL). however the collector sits at 0.7v. * the implications of that for the 2nd transistor is: it can't switch on. * therefore, the 2nd transistor, being "off", has its own resistor up at VCC-3V3.
when the input is at VREFTTL (or close to it):
* 1st transistor is "off", *BUT* is acting as a diode from base to collector. * this results in (VREFTTL-0.7v) going into the 2nd transistor's base * that makes the 2nd transistor switch ON * that results in current flow across the 2nd transistor * that makes the saturation voltage from collector to emitter 0.3v which is what's needed to have BOOT0 at CMOS logic level "0".
anyone see any flaws?
l.