On Dec 25, 2017, at 05:52, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sun, Dec 24, 2017 at 10:29 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Concerning the keepouts under the connector:
- At the north boundary I would pull the edge up a little further north away from the northwestern differential pair.
oh! ha, i just made it the opposite direction :) reason: HHPD acts (kinda) as a GND for that top (HTX2P) and when i did the flood-fill it looked really weird. i'm switching to a couple of different viewing styles (one of them is actually the gerbers, there's an "X-Ray" option.
Looks like a good resolution of the issue.
the top 2 VIAs right next to HTX2P are too far away, and the 15mil-to-GND-keepout condition makes things unbalanced. see proposed GREEN new via placements and YELLOW track to correct that.
I see how it is unbalanced with respect to the two differential pairs--the outside conductors had close to 15mil clearance to ground but the inside conductors had only the distance to the next pad (which was considerably less, ~7mil?). So I applaud the change to make it more symmetric.
when i show X-ray-mode gerbers layers 1 & 2 i mark in yellow at top a proposed modification, look good? you can see to pin 4 there is that GND via, the shape of the hole gets really weird / sharp edges there.
I'm not seeing the weird / sharp edges so you must have fixed them?
also i'm aware that the layer 2 and 5 bottom-most curved-shaped-keepout-holes are about 1 mil too far to the left, see yellow (SE corner) where i'll move them both over.
Again, I'm not seeing a problem so you must have fixed it.
- At the west boundary I see your point regarding layers 4 and 5.
Looks like you have made a good solution. I suppose you could add 5mil additional overlap. How much overlap does it currently have?
currently arouuund 9mil roughly.
How much opening from the edge of the keepout on layer 4 to the edge of the closest connector pads?
around 4mil. tracks are 5mil so can use that as a scale.
In that case I think you have done enough. The overlap looks good.
Some of the adjustments on layer 6 might be taken care of by modifying the net groups to create an "HDMI High-Frequency" group which contains only the differential pairs {HTX2P, HTX2N, HTX1P, HTX1N, HTX0P, HTX0N, HTXCP, HTXCN}, apply the 15mil conditional clearance rule to that group.
that's what's already done :)
oh, except to VIAs i kept it at 5mil, now i remember. 15 mil to landing pads, 15 mil to tracks, 5mil to VIAs i think this was because i didn't want the holes made by VIAs to be too large. what you think? make them 15mil too?
I'm not as worried about the holes left by the vias on the east (connector) end as the west (processor) end of the differential pairs if we expanded clearance to 15mil. I'm guessing we have more current flowing through layers 2,4,5 over there. I guess the question boils down to, "Where are the power sources and sinks (including decoupling capacitors) relative to the HDMI high-frequency signal vias?" If the vias make holes on a line connecting power sources to sinks, then we need to either make sure there is plenty of copper providing a path around the holes or minimize the size of the holes.