arm-netbook

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1076 discussions

travelling
by Luke Kenneth Casson Leighton 29 Oct '19

29 Oct '19

On Tuesday, October 29, 2019, Jacob Lifshay <programmerjake(a)gmail.com> wrote: > On Mon, Oct 28, 2019, 22:08 Luke Kenneth Casson Leighton <lkcl(a)lkcl.net> > wrote: > > > Apologies I am currently travelling and also getting set up to go to > Costa > > Rica to meet TEC University, there are a couple other really critical eco > > conscious projects other that the processor and the EOMA68 one that need > to > > get kicked into high gear. > > > > No problem. just don't fall for the trap of doing too many things to do any > of them effectively. :) Got really nice team this time. Been planning for about 12 years. > > Safe travels. > > These involve transportation: both the vehicles themselves, as well as the > > powertrain. I am presently working hard to do the CAD Model on a > variable > > compression ratio multifuel SIMPLE and libre engine with extremely high > > efficiency, as well as kickstart an ebike conversion project that will > > dovetail into a "mobile battery and distributed internet franchise". > > > > Neat! And (surpriise) the processor will end up in the lithium battery packs, and so will an EOMA68 Card > The multifuel engine is intended for a TRIBRID drivetrain, involving > > electrolysis during braking instead of damaging batteries (yes, regen > > damages batteries) then injecting the mixed hydrogen and oxygen into the > > engine. > > > > I think you may run into issues with needing a massive electrolysis cell to > absorb the full braking power, since electrolysis needs low current/area in > order to not waste a lot of power on overpotential or damage the > electrodes. Correct! Bill Ross is the inventor of exactly that. He uses Potassium Hydroxide as a catalyst, and nickel plates with 0.004 in clearance, 2.5v @ 50 A and you get enough hydrogen to add to a family sized car. > You may want to check out using supercapacitors instead, as a temporary > energy storage mechanism, No, because the voltage varies with current, naking it extremely difficult, electronically, to deliver the power back. What the supercapacitors *are* good for is fronting on the batteey packs, directly at the controller. The decreased resistance results in power being first delivered *from the capacitor* which protects the battery from high load. > since they have a very high power rating (in the > range of 1000x batteries) due to not being based on a chemical reaction. > additionally, supercapacitors don't need additional plumbing and don't need > water refills. they also can skip the big energy loss of > internal-combustion engines which are usually less than 50% efficient. Funny you should mention that. Google 6 stroke engine wikipedia https://www.youtube.com/watch?v=IovhYvKpFRQ Patents from 1880 and 1921 show that water flashing to steam when injected at TDC will not only cool the cylinder but will actually do "work". As efficiency is a direct product of temperature differentials, the 2 extra strokes can result in a whopping FORTY PERCENT efficiency improvement. The processor and EOMA68 have been part of a long term strategy that is > > just about to take off. However obviously I cannot do everything so have > > had to stop technical work on the processor whilst getting the engine etc > > up and running. > > > > Ok, hopefully you will be available to help out with some of the more > important decisions such as deciding if we should switch to Power or not. Of course. > > The purpose of going to TEC University is to see if they are willing to > > handle some of the projects. > > > > that would be nice Yeh we need extra (motivated) people. Funnily enough, the Intel building in Costa Rica happens to be empty at the moment... :) L. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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travelling
by Luke Kenneth Casson Leighton 29 Oct '19

29 Oct '19

Apologies I am currently travelling and also getting set up to go to Costa Rica to meet TEC University, there are a couple other really critical eco conscious projects other that the processor and the EOMA68 one that need to get kicked into high gear. These involve transportation: both the vehicles themselves, as well as the powertrain. I am presently working hard to do the CAD Model on a variable compression ratio multifuel SIMPLE and libre engine with extremely high efficiency, as well as kickstart an ebike conversion project that will dovetail into a "mobile battery and distributed internet franchise". The multifuel engine is intended for a TRIBRID drivetrain, involving electrolysis during braking instead of damaging batteries (yes, regen damages batteries) then injecting the mixed hydrogen and oxygen into the engine. The processor and EOMA68 have been part of a long term strategy that is just about to take off. However obviously I cannot do everything so have had to stop technical work on the processor whilst getting the engine etc up and running. The purpose of going to TEC University is to see if they are willing to handle some of the projects. L. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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HAK_MTL 2019 documentary
by Luke Kenneth Casson Leighton 02 Oct '19

02 Oct '19

https://vipmovies.to/watch/x2UL5u/hak_mtl-2019 57 minutes in. had completely forgotten about hopeconf2016 -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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need help finding EU Citizens to help with NLNet Funding proposals
by Luke Kenneth Casson Leighton 30 Sep '19

30 Sep '19

https://git.libre-riscv.org/?p=crowdsupply.git;a=blob;f=updates/020_2019aug… I now have *seven* NLNet Funding proposals in and I urgently need four EU Citizens to be part of each project. Whether you actually do anything is entirely up to you. The way it works is that NLNet has been funded by thr EU Horizon 2020 Programme. Thus they need at least one member of the team to be an EU Citizen. They do not have to be *resident* in the EU, just gave an EU address. This includes the UK fir the next month. The important thing to note is that this is not a contract, it is a Memorandum of Understanding. There are no penalties and no committment. If you can help please do get in touch, I will need to be able to say "yes" on each project over the next 3 weeks. If you know someone.who can help please do ask around. Thx. L. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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slashdot article submitted about NLNet Grants for Libre-RISCV SoC
by Luke Kenneth Casson Leighton 29 Sep '19

29 Sep '19

https://slashdot.org/submission/10462238/libre-risc-v-3d-cpugpu-applying-fo… please do upvote... l.

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Re: [Arm-netbook] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
by Luke Kenneth Casson Leighton 25 Sep '19

25 Sep '19

On Tue, Sep 24, 2019 at 1:06 PM Staf Verhaegen <staf(a)fibraservi.eu> wrote: > Have yo guys looked at the pipeline feature of Wishbone B4 ? What is missing there to make streaming possible ? hagen mentioned (offlist) that the broadcast mode of wishbone b4 could indeed be used. he'd like to do a write-up / proposal and i am happy to help him review it. l.

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Re: [Arm-netbook] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
by Luke Kenneth Casson Leighton 24 Sep '19

24 Sep '19

On Tuesday, September 24, 2019, Staf Verhaegen <staf(a)fibraservi.eu> wrote: OK, let me mention I have for my Retro-uC currently nmigen Wishbone code. Great! > > I use it to make an arbiter between JTAG and the CPU cores on the design > (Z80, MOS6502 and Motorola 68000) that can do a read/write for each cycle. > Plan is top commit code to my gitlab repo after ORConf. > Dan from ZipCPU would say that I still have to formally verify the code > though... . Yes. Ah it just occurred to me to get in touch with him again, see if he would like to help with the formal proofs proposal. Looks like you might get your "wish" after all, David :) L. > greets, > Staf. > > -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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Re: [Arm-netbook] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
by Luke Kenneth Casson Leighton 24 Sep '19

24 Sep '19

On Tue, Sep 24, 2019 at 9:55 AM Hagen SANKOWSKI <hsank(a)posteo.de> wrote: > The main difference between AMBI AXI and Wishbone is the streaming > capability. AXI can stream data, just with repetition stages, without > handshake signals. So, it would be easier and more sustainable to > bring-up Wishbone to the next level by standardize a similar streaming > feature. And yes, there are a lot of cores which using AMBA AXI which > had to be partly re-written for Wishbone. But currently, there is no > alternative, or as the German chancellor Merkel likes to say: > "alternativlos". With added streaming feature to Wishbone, we would get > an alternative full-featured SoC Bus and Designers could fix their bad > AMBA AXI bus interfaces.. great: this sounds like a perfect *additional* Research Project which someone [else] could put in a request for funding. once it is available, we can look at converting the code over to use it, and converting any peripherals to use it. or, if someone [else] wants to include the Libre RISC-V SoC peripheral set as a possible suite of examples to convert (which would help justify a budget of EUR 50,000) they are welcome to do so. the relevance of the streaming capability is that we need an I2S Audio Bus. i can help with a write-up: unfortunately i am hitting an _additional_ limit of EUR 250,000 per person for overall projects submitted, so cannot be the one to submit it. l.

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Re: [Arm-netbook] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
by Luke Kenneth Casson Leighton 24 Sep '19

24 Sep '19

On Mon, Sep 23, 2019 at 9:48 AM David Lanzendörfer <leviathan(a)libresilicon.com> wrote: > > Hi Luke > In order to be truly libre, you've got to remove AXI from the RISC-V > implementation and replace it with TileLink or another bus, which isn't > patented by a company. > Also I would strongly discourage you from using ARM patented solutions, > this might most certainly come back in the future to hunt you. appreciated, david: the main issue that we have is, with implementing a GPU and VPU and CPU all in one, it's going to be unavoidable to run into 3D patents, Video patents, you name it, we'll be hitting it. from ICubeCorp alone - one company that i know of for certain created a similar "Hybrid" CPU/GPU/VPU, we'll be hitting up to *seventeen* patents: https://patents.google.com/?q=ICubeCorp&oq=ICubeCorp broadcom's videocore IV, which is based on the ARC core (bought by synopsys), likewise has a whole stack of patents: ARC's primary business was - is - licensing identical to ARM except embedded and not as high-profile, with specialisation in Video SIMD instructions. to even *try* to avoid these is just completely pointless: the entire design would be so hamstrung as to be utterly commercially useless, and, worse than that, we'd be taking on far more work and would completely miss the goal as a result, missing out on additional funding opportunities that would enable us to actually get to first silicon. in short: if we're adding AXI to the list of patents to avoid, because we take on the additional responsibility of avoiding patents, we also have to add the entire MASSIVE list of other patents in Video Acceleration, 3D Acceleration, processor core design, and so on, and it's just completely impractical. some alternative strategies present themselves: (1) if a customer (licensee) is presented with a patent demand, we can look at prior art and arrange for the patent to be invalidated. we have nothing to lose. enough of these being successful will cause large patent holders to freak out and back the hell off. (2) join a patent pool. like the linux foundation, except for hardware. the newly-formed Open 3D Graphics Alliance is a good place to start from, here. (3) get to first silicon, get chips sold, get investment, *then* fund a new ASIC design that avoids all known patents. bottom line: we have to be realistic, and pick the best technology for the job. TileLink, with its low level of adoption, Is Not It (and using chisel3 is not an option for this processor). Wishbone, whilst we may need some wb2axi bridges in order to avoid having to do major rewrites, just doesn't cut it as far as complex multi-way routing is concerned. l.

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NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
by Luke Kenneth Casson Leighton 23 Sep '19

23 Sep '19

[please do remove all but libre-riscv-dev when replying, thx] https://libre-riscv.org/nlnet_proposals/ A series of funding proposals, each for EUR 50,000, have been submitted to NLNet. These are for charitable donations and may be given to either individuals or to Universities (not to Corporations) for completion of an allotted milestone. The basic idea is to think through and plan for commercial completion all of the tasks that will make the Libre RISC-V SoC a success. It's a lot! We have the following: - a second Vulkan 3D driver, which will be a port of AMDVLK. similar to swiftshader, for the Libre RISCV SoC, except taking into account the Vectorisation, predication and custom accelerated opcodes. - a video acceleration initiative: with NEON assembler being up to the job of decoding 720p video on recent ARM64 processors, the idea is to design instructions that will do the job and then follow through getting the code upstream. - two related proposals which, in combination, will result in an actual 180nm ASIC being taped out at TSMC. - a formal mathematical proof of the hardware design, proving inviolate guarantees of its correctness. this because although auditing the code is possible, it is both laborious, error prone, and could be compromised. mathematical proofs may be run by anyone and are inviolate. - an augmentation of gcc to support the processor’s parallel and vectorisation capabilities. Yes, really: 180nm ASICs only cost around EUR 600 per square millimetre, and with around 20 or so mm^2 it is completely within the realm of possibility for an NLNet Grant to fund a test ASIC. With each square millimetre being around 40,000 gates in 180nm, that's around 800,000 gates, which is enormous. We would then have a proven ASIC, and moving up to 40nm or below, which would require around the USD 2m mark, is a far less risky proposition. The irony is that whilst these funding proposals are quite easy to write, we also need to find people willing to do the work! In particular, we need at least one EU Citizen per project. They do not have to be permanently resident in the EU, they do however need an EU residence. Yes this includes the UK at the time of writing. This is an extremely important strategic project that puts you - software libre developers - in the driving seat of modern technology instead of picking up the reverse engineering crumbs that fall from the Corporate table with at least a 2 year delay. If you would like to help and actually receive donations (directly transferred) from NLNet for doing so, please do contact me directly or on libre-riscv-dev. L. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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