<br>> ground layer next to the DDR3 tracks to get the characteristic impedance<br><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">
> correct and also to give good return path. Something like:<br>
> L1 : tracks , L2 : ground, L3 : power, L4 : tracks, L5 : GND, L6 : tracks<br>
<br>
</div> that looks about right.<br>
<div class="im"><br>
> Since you already have done it,<br>
<br>
</div> i have not. what i have done is asked SoC manufacturers to supply </blockquote><blockquote class="gmail_quote" style="margin:0pt 0pt 0pt 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
full EVB schematics. i have then NOT ONCE MADE ONE SINGLE ALTERATION<br>
TO THE DDR3 LAYOUT, precisely because i know that it is beyond my<br></blockquote><div class="h5"><br>Hi Luke, This is the only uncertain stuff I think, I go by the old saying "When you don't get what you want, what you get is experience". I have no other option. <br>
If you find time, please check for mistakes in the DDR part of the schematic. I have uploaded with some more changes. I have the A13 core board from WITS, that gives some idea about the AXP209 layout.<br><br>ajith<br><br>
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</div></div><br><br clear="all"><br>-- <br>Dr. Ajith Kumar B.P.<br>Scientist SH<br>Inter-University Accelerator Centre<br>Aruna Asaf Ali Marg<br>New Delhi 110067<br><a href="http://www.iuac.res.in" target="_blank">www.iuac.res.in</a><br>
Ph: (off) 91 11 26893955 (Ext.230)<br> (res)91 11 26897867<br> (mob) 91 9868150852<br>