<div dir="ltr"><div class="gmail_extra"><br><div class="gmail_quote">2013/2/25 joem <span dir="ltr"><<a href="mailto:joem@martindale-electric.co.uk" target="_blank">joem@martindale-electric.co.uk</a>></span><br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
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</div></blockquote></div><br>Not sure about it, documentation about the core (FA626TE from Faraday-tech) says that there is an MMU and it is compatible to the ARM MMU.</div><div class="gmail_extra"><br></div><div class="gmail_extra">
"The Memory Management Unit (MMU) provides the address translation and permission check mechanism for memory access. The FA626TE MMU implements the two-level TLB structure. Level-1 TLB includes an ITLB for the instruction access look-up and a DTLB for the data access look-up. Both look-ups are 8-entry fully-associate. Level-2 TLB (UTLB) is a unified 2-way set-associate TLB structure. TLBs cache the most recently used page descriptors for the address translation, which greatly improves the overall performance. Once UTLB misses, the page table walk will be completed automatically by the hardware.</div>
<div class="gmail_extra">The FA626TE MMU is compatible with the MMU defined in the ARM Architecture Reference Manual, second edition, with some minor differences due to the inherent differences in cache and TLB implementation"</div>
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