<div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> the DDR3 RAM circuit, if you do not use PADS, and do not keep those<br>
DDR3 connections EXACTLY the same, you will be in for a bit of a shock<br>
when it comes to doing the development of the A10 board.<br>
<br></blockquote><div><br></div><div>why? let's not act like chinese factory with copy and paste designs :)</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
wits-tech's PADS layout has done the hard part. if you deviate from<br>
that you will need to spend several man-months replicating that costly<br>
work.<br>
<div class="HOEnZb"><div class="h5"><br></div></div></blockquote><div><br></div><div>this is what I read on their PDF schematic:</div><div><br></div><div>DQ0-7、DQM0、DQS0 Length matching 100mil</div><div>DQ8-15、DQM1、DQS1 Length matching 100mil</div>
<div>DQ16-23、DQM2、DQS2 Length matching 100mil</div><div>DQ24-31、DQM3、DQS3 Length matching 100mil</div><div>DA、CONTROL、CK Length matching 300mil</div><div>DQSn、DQSn# Differential pairs Z0= 100 ohm,Length matching 10mil</div>
<div>CK、CK# Differential pairs Z0= 100 ohm,Length matching 10mil</div><div><br></div><div>and this is pretty much same as on the other DDR3 requirements I've seen for other processors like AM335X for instance</div><div>
seems to me not hard to accomplish simple rules: keep length same and impedance as required and there should be no issues with proper ground planes. It would be good to have look at what they did, but I can see it even on Mele1000 I have as the signal routing is on the top and bottom with ground planes on the inner layers</div>
<div><br></div><div>Tsvetan</div></div>