<br><br><div class="gmail_quote">On Wed, May 23, 2012 at 11:26 AM, sysfwlab <span dir="ltr"><<a href="mailto:sysfwlab@gmail.com" target="_blank">sysfwlab@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hello everybody,<br>
<br>
My final goal is to modify uboot-allwinner to support sun3i platform.<br>
After successfully building a minimal application ("Dummy Sun3i<br>
bootloader") that blink a led and after manage the UART0, i improve it<br>
with small clocking, math, printf, dump tools, etc..and i learn a lot of<br>
things.<br>
(Here is a synthesis in french, but ascii schematics are in english<br>
<a href="http://www.sysfwlab.com/?cat=8" target="_blank">http://www.sysfwlab.com/?cat=8</a>)<br>
<br>
Now, i want to play with SD/MMC driver. I do a A10 source analysis and i<br>
got a lot of information but i need help, i got some questions and need<br>
your experience...<br>
<br>
You can found here A10 uboot SD/MMC driver analysis synthesis (if need):<br>
<a href="http://www.sysfwlab.com/?p=564" target="_blank">http://www.sysfwlab.com/?p=564</a><br>
<br>
You can found here F20 uboot SD/MMC driver adaptation analysis synthesis<br>
(if need) :<br>
<a href="http://www.sysfwlab.com/?p=585" target="_blank">http://www.sysfwlab.com/?p=585</a><br>
<br>
Here is my questions, hope someone can help me :<br>
<br>
1 - I found the F20 controller base address SDCx_BASE and i know the<br>
SD/MMC registers offsets for A10 (gctrl,clkcr,timeout,with,etc...) do<br>
you think is reasonable to think the SD/MMC controler is the same on F10<br>
and A10 so registers offset can be identicale ?<br>
<br></blockquote><div>I can tell you F20 and A10 has the same SD controller. But the CCU is different.</div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
2 - My main probleme is the main clocks registers.<br>
On A10 we got 4 clock registers, one clock register per controller (ex:<br>
SDC0_CLK : 0x01c20088 for SDC0_BASE : 0x01c0f000 )<br>
On F20 we got only 2 clock registers, one clock register for two<br>
controllers .<br>
(ex: SDC01_CLK : 0x01c20018 for SDC0_BASE : 0x01c0f000 and SDC1_BASE :<br>
0x01c10000)<br>
<br>
Here is what i known on a clock register for A10 (it's suffisant to<br>
enable it):<br>
-------------------------------------------------<br>
Register : SDC0_CLK - Base : 0x01c20088<br>
SDC1_CLK 0x01c2008c<br>
SDC2_CLK 0x01c20090<br>
SDC3_CLK 0x01c20094<br>
-------------------------------------------------<br>
BITS | DESCRIPTION<br>
-------------------------------------------------<br>
0 \<br>
1 | Divider - 011: 3, 100: 4<br>
2 /<br>
3<br>
4<br>
...<br>
23<br>
24 1 ???<br>
25<br>
...<br>
30<br>
31 1 ???<br>
=================================================<br>
<br>
Did you get and idea ? Do you think the register organisation for F20 is<br>
the same expect i manage 2 controllers at once ?<br>
(Did you ever see this on other CPU ?)<br>
<br>
3 - Controller frequency<br>
I compute uboot start A10 CPU at 504MHz and PLL5 witch drive SD/MMC<br>
controllers at 360 MHz, do you think is something common ?<br>
<br>
4 - Linux & Sun3i SD/MMC driver<br>
I dont find SD/MMC allwinner reference on linux-allwinner tree, but i<br>
know it can read SD, can someone help me to find and entry point ?<br>
(I ever read /drivers, /includes, but nothing about allwinner register,<br>
etc...it go throught drivers/platform structures callback and callback<br>
and callback...:) and nothing about mmc and low level allwinner<br>
acces....please help ) it's a standard component ? (like UART is 16555<br>
clone ?)<br>
<br>
5 - More generally if someone can give me the SD/MMC map register for<br>
F20 it will be the best but all information, idea and expericence are<br>
well come...Please Mr Allwinner, open this registers :), please... </blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
<br>
6 - Subsidiar : I got a main clock named "VE_PLL" (in top off the clock<br>
hierarchy, near "CORE_PLL", do you now what does "VE" mean ?<br>
(Video Engine ? ...it seame to be an important module but....)<br>
<br>
Thanks a lot in advance,<br>
(and sorry for expression)<br>
<br>
Bin<br>
<br>
<br>
_______________________________________________<br>
arm-netbook mailing list <a href="mailto:arm-netbook@lists.phcomp.co.uk">arm-netbook@lists.phcomp.co.uk</a><br>
<a href="http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook" target="_blank">http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook</a><br>
Send large attachments to <a href="mailto:arm-netbook@files.phcomp.co.uk">arm-netbook@files.phcomp.co.uk</a><br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><font face="'trebuchet ms', sans-serif">Keep simple, stay foolish.</font>
<div> </div><br>