<br><br><div class="gmail_quote">2012/2/8 lkcl luke <span dir="ltr"><<a href="mailto:luke.leighton@gmail.com">luke.leighton@gmail.com</a>></span><br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
folks, hi,<br>
<br>
i've not mentioned this before, publicly, but some time last year when<br>
this initiative was still being considered we were finding it so<br>
ridiculously difficult to find cooperative CPU companies that we gave<br>
serious consideration to putting a deal together to create a new<br>
(entirely software-based) SoC that would be entirely FSF-Endorseable<br>
as it would be entirely software-programmable.<br>
<br>
based around something like the ARC 32-bit RISC core (which was a hell<br>
of a lot better than ARM's offerings at the time), the idea was to put<br>
at least 4 of them down in 28nm, where they would quite happily run at<br>
at least 1.5ghz.<br>
<br>
the problem was that ARC's RISC core design wasn't SMP capable, and<br>
the team behind it didn't feel comfortable doing SMP cache coherency.<br>
we _did_ come up with a mad and very simple scheme to do cache<br>
coherency as a software interrupt (similar to how MMU page-swapping is<br>
done) and even discussed it on LKML thanks to alan cox and some input<br>
from another guy from intel, it turns out to have been a workable<br>
scheme.<br>
<br>
... but, we didn't pursue it.<br>
<br>
some time last month i went "hang on a minute, maybe now's a better<br>
time" so i've done a draft of the interfaces (DDR3 RAM will be<br>
included) the number of pins required is surprisingly low, which will<br>
get the cost down.<br>
<br>
i'd therefore greatly appreciate some help reviewing the pinouts. the<br>
company that i've found that has an alternative 32-bit RISC core not<br>
only has SMP cache coherency already done, but also they have an<br>
absolutely amazing set of Instruction extensions, including DSP,<br>
Audio, Video, Base-band (for RF handset processing) and much more.<br>
the plan is, therefore, to target this CPU at a very very wide range<br>
of markets, based on it having:<br>
<br>
* 8 CPUs at 1.2ghz or above<br>
* SMP Cache Coherency<br>
* 32-bit DDR3 1333mhz RAM (with a 2nd version having 2 DDR3 interfaces)<br>
* virtually everything software-programmable (with the exception of<br>
CABAC decode)<br>
<br>
meaning that it will do 3D graphics _and_ 1080p Video entirely in<br>
software. the interfaces i've selected so far will include:<br>
<br>
* HDMI Out _and_ In<br>
* 24-pin RGB/TTL<br>
* 2-channel LVDS<br>
* 2 PCIe (2-lane each)<br>
* USB-OTG, USB-2 and USB-3<br>
* SATA-3<br>
* NAND controller (8-bit with 4-way CS)<br>
* 3 SD/MMC interfaces<br>
* 3 SPI interfaces<br>
* 3 UARTs, 3 IIC interfaces, CAN-Bus, 2 PS/2, Touchscreen, 3 PWMs<br>
* 2 MPEG Transport Stream Interfaces<br>
* Smartcard Interface<br>
<br>
that means that it could be used in at least the following products:<br>
<br>
* Laptops, Netbooks, Tablets, Desktops, PCs, NAS-Boxes<br>
* PVRs, TVs, Set-Top Boxes, Satellite Decoders<br>
* Smartphones, Base Stations, GNU/Radio SDR Products<br>
<br>
bearing in mind that this will be out some time in middle of 2013, if<br>
it's started soon, i could reallly do with some help reviewing the<br>
interfaces and capabilities, to make sure i've got it right.<br>
<br>
tia,<br>
<br>
l.<br>
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Send large attachments to <a href="mailto:arm-netbook@files.phcomp.co.uk">arm-netbook@files.phcomp.co.uk</a></blockquote><div><br></div><div>Hi, Luke,</div><div><br></div><div>The direction that you are evaluating is similar to that of NVidia. According to the source (full of rumors and not the most credible one according to me) a future product of Nvidia with code name Denver (or Tegra 5) is a SoC that contains together CPU and GPU. The CPU side will be <font class="Apple-style-span" face="arial, helvetica, sans-serif">"<span class="Apple-style-span" style="color:rgb(17,17,17);font-size:13px;line-height:19px;background-color:rgb(255,255,255)">a software/firmware based ‘code morphing’ CPU like Transmeta". (The latter had VLIW-like architecture that relies on software compiler). The release date of Denver is planned in 2013/2014 time frame. :)</span></font></div>
<div><font class="Apple-style-span" color="#111111" face="arial, helvetica, sans-serif"><span class="Apple-style-span" style="line-height:19px">If the free/open source software developers have enough space to play with the processor, proposed by you, they will not </span></font><span class="Apple-style-span" style="font-family:arial,sans-serif;font-size:13px;white-space:nowrap;background-color:rgb(255,255,255)">let you down.</span><span class="Apple-style-span" style="color:rgb(17,17,17);font-family:arial,helvetica,sans-serif;line-height:19px"> More over if you give them more freedom than NVidia solution. So I am full of positivism about your direction. </span></div>
<div><font class="Apple-style-span" color="#111111" face="arial, helvetica, sans-serif"><span class="Apple-style-span" style="line-height:19px"><br></span></font></div><div><font class="Apple-style-span" color="#111111" face="arial, helvetica, sans-serif"><span class="Apple-style-span" style="line-height:19px">The source: </span></font><a href="http://semiaccurate.com/2011/08/05/what-is-project-denver-based-on/">http://semiaccurate.com/2011/08/05/what-is-project-denver-based-on/</a></div>
<div><br></div></div><br><div>Regards,</div><div><br></div><div>Iliya</div>