From doark at mail.com  Wed Jan  1 20:37:33 2020
From: doark at mail.com (David Niklas)
Date: Wed, 1 Jan 2020 15:37:33 -0500
Subject: [Arm-netbook] Libre RISC-V -- I mean OpenPower M-Class GPU
 update
In-Reply-To: <CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
References: <20191231140447.243978ef@Phenom-II-x6.niklas.com>
	<CAPweEDyf=o9EM=aN+rPmBGWBU8WZEB4av1BX_+MGCs41trUCoA@mail.gmail.com>
	<20191231163027.2304f5d0@Phenom-II-x6.niklas.com>
	<CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
Message-ID: <20200101153733.76086995@Phenom-II-x6.niklas.com>

On Tue, 31 Dec 2019 23:02:51 +0000
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> On 12/31/19, David Niklas <doark at mail.com> wrote:
>
> > Maybe I have not been clear, how does signing an agreement or joining
> > UC "vet" people?
> > I always thought that my code/schematics vetted me as a fool or a wise
> > man.
>
> it's not that simple when it comes to collaboration where it really
> matters if incompatibilty is hosed.
>
<snip>

That's a really interesting reply. Do you mean that there is no way to
pretest changes, say with an FPGA and only Silicon will prove the design?
Or is there no ongoing testing? Or what?

Thanks,
David


From lkcl at lkcl.net  Wed Jan  1 22:09:38 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Wed, 1 Jan 2020 22:09:38 +0000
Subject: [Arm-netbook] Libre RISC-V -- I mean OpenPower M-Class GPU
	update
In-Reply-To: <20200101153733.76086995@Phenom-II-x6.niklas.com>
References: <20191231140447.243978ef@Phenom-II-x6.niklas.com>
	<CAPweEDyf=o9EM=aN+rPmBGWBU8WZEB4av1BX_+MGCs41trUCoA@mail.gmail.com>
	<20191231163027.2304f5d0@Phenom-II-x6.niklas.com>
	<CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
	<20200101153733.76086995@Phenom-II-x6.niklas.com>
Message-ID: <CAPweEDyoATG_-6ugXZk66Cb4C5DaCx7wqOHeSghjerCFom-ubQ@mail.gmail.com>

On 1/1/20, David Niklas <doark at mail.com> wrote:
> On Tue, 31 Dec 2019 23:02:51 +0000
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>> On 12/31/19, David Niklas <doark at mail.com> wrote:
>>
>> > Maybe I have not been clear, how does signing an agreement or joining
>> > UC "vet" people?
>> > I always thought that my code/schematics vetted me as a fool or a wise
>> > man.
>>
>> it's not that simple when it comes to collaboration where it really
>> matters if incompatibilty is hosed.
>>
> <snip>
>
> That's a really interesting reply. Do you mean that there is no way to
> pretest changes, say with an FPGA and only Silicon will prove the design?
> Or is there no ongoing testing? Or what?

no, it's that if the Trademark Holder refuses to respect Trademark
Law, failing repeatedly to respond to reasonable and in-good-faith
requests to have taken into consideration the unique Libre-transparent
*business* circumstances that were never, in any way shape or form
envisaged by the Founders at the time of the creation of the
Membership Agreement - the one that every other *business* is
perfectly happy to sign because no other business that signed the
Agreement gives a flying fuck about transparency and trust for the
benefit *of end-users* (not shareholders) - then the *technical*
aspects you describe - testing, pretesting, silicon, FPAGs - all that
is absolutely and utterly irrelevant.

the collaboration that is in place, and which is otherwise
successfully taking place, is taking place behind *closed doors*,
where we, as Libre Businesses, are told, basically, "sign this
agreement which entirely compromises your business model, or go fuck
yourself".

by complete contrast...

the OpenPower Foundation's Director, Hugh Blemings, is someone who has
worked with Libre Developers (he himself is one) for over two, nearly
three decades.

*he* was the one that told *me* that the OpenPower Foundation Members
have created a Membership Agreement that is specifically designed to
allow Libre Businesses to be "happy" with its terms and conditions.

l.


From paul at boddie.org.uk  Wed Jan  1 23:30:41 2020
From: paul at boddie.org.uk (Paul Boddie)
Date: Wed, 01 Jan 2020 23:30:41 +0000
Subject: [Arm-netbook] Libre RISC-V -- I mean OpenPower M-Class GPU
	update
In-Reply-To: <CAPweEDyoATG_-6ugXZk66Cb4C5DaCx7wqOHeSghjerCFom-ubQ@mail.gmail.com>
References: <20191231140447.243978ef@Phenom-II-x6.niklas.com>
	<CAPweEDyf=o9EM=aN+rPmBGWBU8WZEB4av1BX_+MGCs41trUCoA@mail.gmail.com>
	<20191231163027.2304f5d0@Phenom-II-x6.niklas.com>
	<CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
	<20200101153733.76086995@Phenom-II-x6.niklas.com>
	<CAPweEDyoATG_-6ugXZk66Cb4C5DaCx7wqOHeSghjerCFom-ubQ@mail.gmail.com>
Message-ID: <21d7632c1602a2e880c2c681acd9b07e@boddie.org.uk>

On 2020-01-01 22:09, Luke Kenneth Casson Leighton wrote:
> 
> the collaboration that is in place, and which is otherwise
> successfully taking place, is taking place behind *closed doors*,
> where we, as Libre Businesses, are told, basically, "sign this
> agreement which entirely compromises your business model, or go fuck
> yourself".

I haven't followed what goes on with RISC-V licensing, but it rather 
sounds like there are vested interests who want to retain control and to 
leverage their inherent advantage as developers of the technologies 
concerned. This is a pretty familiar story from the world of standards, 
even Internet standards, where companies effectively "front-run" 
standards by loading them up with descriptions of their own 
technologies, effectively requiring standards implementers to play 
catch-up all the time.

This latter strategy is not quite the same thing as, say, people being 
gatekeepers to a CPU architecture, but it is part of a more general 
phenomenon of stacking the odds in one's own favour and disadvantaging 
outsiders. A more mundane example would be any one of numerous 
corporate-run Free Software projects that demand copyright or 
comprehensive licensing assignments from contributors, and who make it 
tediously difficult to get code upstream, all because the company's 
needs supposedly override all others.

> by complete contrast...
> 
> the OpenPower Foundation's Director, Hugh Blemings, is someone who has
> worked with Libre Developers (he himself is one) for over two, nearly
> three decades.
> 
> *he* was the one that told *me* that the OpenPower Foundation Members
> have created a Membership Agreement that is specifically designed to
> allow Libre Businesses to be "happy" with its terms and conditions.

Maybe ARM's success is a corrupting influence when companies and 
organisations try to monetise hardware architectures, but ARM only got 
into its lucrative position through a combination of good luck and a 
fervour for licensing things, the latter only ever coming about as some 
kind of correction for ARM's corporate predecessor's obsession with 
keeping everything proprietary and trying to use such proprietary 
technologies to their own exclusive competitive advantage. It will be 
interesting to see how the different initiatives (RISC-V, OpenPower, 
MIPS...) evolve to respond to openness concerns and the need to 
cultivate interest in their offerings more generally.

Paul


From lkcl at lkcl.net  Thu Jan  2 00:28:03 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Thu, 2 Jan 2020 00:28:03 +0000
Subject: [Arm-netbook] Libre RISC-V -- I mean OpenPower M-Class GPU
	update
In-Reply-To: <21d7632c1602a2e880c2c681acd9b07e@boddie.org.uk>
References: <20191231140447.243978ef@Phenom-II-x6.niklas.com>
	<CAPweEDyf=o9EM=aN+rPmBGWBU8WZEB4av1BX_+MGCs41trUCoA@mail.gmail.com>
	<20191231163027.2304f5d0@Phenom-II-x6.niklas.com>
	<CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
	<20200101153733.76086995@Phenom-II-x6.niklas.com>
	<CAPweEDyoATG_-6ugXZk66Cb4C5DaCx7wqOHeSghjerCFom-ubQ@mail.gmail.com>
	<21d7632c1602a2e880c2c681acd9b07e@boddie.org.uk>
Message-ID: <CAPweEDzvQjjUUxXZ7WQziTGfT9OpqiEDRQQH8uZeC5DjpO-TZg@mail.gmail.com>

On 1/1/20, Paul Boddie <paul at boddie.org.uk> wrote:
> On 2020-01-01 22:09, Luke Kenneth Casson Leighton wrote:
>>
>> the collaboration that is in place, and which is otherwise
>> successfully taking place, is taking place behind *closed doors*,
>> where we, as Libre Businesses, are told, basically, "sign this
>> agreement which entirely compromises your business model, or go fuck
>> yourself".
>
> I haven't followed what goes on with RISC-V licensing, but it rather
> sounds like there are vested interests who want to retain control and to
> leverage their inherent advantage as developers of the technologies
> concerned.

this resonates with the behaviour i've seen.  it's also that, well,
they just don't care.  i've witnessed around a dozen people, now,
including several professors from highly-regarded world-renowned
universities, just "give up" and walk away from the mailing lists.

on the other hand when an employee from qualcomm innnocently /
accidentally cross-posted a question onto the isa-dev mailing list,
warnings were issued "there's more at stake, here" which basically
implied, "shut the fuck up you moron, we want qualcom's money: your
answers, questions and honesty are causing them to become extremely
nervous about using RISC-V".

then, there is the weird behaviour of SiFive, with the promise of
"fixing the problems of other ISAs" then rushing ahead without proper
consultation and "laying down the law".

> This is a pretty familiar story from the world of standards,
> even Internet standards, where companies effectively "front-run"
> standards by loading them up with descriptions of their own
> technologies, effectively requiring standards implementers to play
> catch-up all the time.

yyyup.  that's precisely and exactly what's happened.

> This latter strategy is not quite the same thing as, say, people being
> gatekeepers to a CPU architecture, but it is part of a more general
> phenomenon of stacking the odds in one's own favour and disadvantaging
> outsiders. A more mundane example would be any one of numerous
> corporate-run Free Software projects that demand copyright or
> comprehensive licensing assignments from contributors, and who make it
> tediously difficult to get code upstream, all because the company's
> needs supposedly override all others.

yes, this is uncalled for.  however, as we've learned from the EOMA68
Certification Mark, having a *Certification Mark* behind a standard, for
the protection and safety of users, turns out to be absolutely essential,
*even if* the source code is GPL'd / Libre-Licensed.

i would not have a problem with the RISC-V Foundation if they actually,
properly, truly understood Trademark Law and their legal obligations
and responsibilties.

>> by complete contrast...
>>
>> the OpenPower Foundation's Director, Hugh Blemings, is someone who has
>> worked with Libre Developers (he himself is one) for over two, nearly
>> three decades.
>>
>> *he* was the one that told *me* that the OpenPower Foundation Members
>> have created a Membership Agreement that is specifically designed to
>> allow Libre Businesses to be "happy" with its terms and conditions.
>
> Maybe ARM's success is a corrupting influence when companies and
> organisations try to monetise hardware architectures, but ARM only got
> into its lucrative position through a combination of good luck and a
> fervour for licensing things,

only because they were desperate!  see below... :)

> the latter only ever coming about as some
> kind of correction for ARM's corporate predecessor's obsession with
> keeping everything proprietary and trying to use such proprietary
> technologies to their own exclusive competitive advantage.

funny story: my friend barry worked for LSI Logic, with norman wilson.
the two of them, how can we put it diplomatically...  LSI's goal was,
um, "to make the customer's design actually work".

undiplomatically: ARM's first processors were non-working piles of f*****g s**t.

after they got the ARM7 functional, barry managed to get ARM their
very first license, ever: with Plessey.  they were so happy, they
offered him a job.  barry turned it down: he would have been employee
number 12, and a very rich man, now :)

but ARM - aka ACORN RISC machines (not Advanced RISC Machines) -
basically had zero cash, and at one point was completely unable to pay
its employees (this is like... early 1990s).  they licensed the ARM11
design to Intel for GBP 100,000, unrestricted, royalty-free, in
exchange for a promise from the team that IBM had bought (the DEC
Alpha developers), would "fix all the problems and give the changes
back".

the DEC Alpha developers - whom Intel themselves didn't know what to
do with, so gave them the PXA Project to do - took one look at the HDL
and went "holy f*** this is s**t" and started again from scratch.
they could do so because they had that GBP 100,000 royalty-free
license from ARM, and the contract wasn't worded carefully enough.

thus, the PXA 2xx series became the world's first superscalar
ARM-compatible architecture... *not* the ARM Cortex A8 as ARM keeps
telling everybody :)

several years later, ARM calls up Intel and says, "um... you've been
selling PXA SoCs for some time now, um... where's the source code?"
and of course they replied, "oh, the ARM11 was so shit we ditched it
and started again.  we never actually made any modifications to the
*ARM11* codebase, check the wording of the contract, bye, have a nice
life".

the irony is that the PXA series was so much more powerful and so much
more power-efficient than the Intel Atom processors available at the
same time, the DEC/Alpha aka PXA team was PROHIBITED from releasing
Intel PXA SoCs running above 600mhz.

of course when Marvell bought the PXA designs (minus the DEC/Alpha
team that developed it), they made absolutely no changes whatsover:
all they did was immediately crank the clock rate up to 1.2ghz and
that's what you find in the OpenRD/Ultimate and the Sheeva Plugs.

ARM's *real* story is littered with embarrassing stumbles from one
architectural mess to another.  they've never *actually* designed a
successful processor in their entire corporate history!

the ARM7 was a mess that LSI Logic had to diplomatically fix

the ARM9 was something that was developed by someone else and offered
to them (i don't know its history).

the ARM11 was developed by a Kiwi who just turned up one day, no
interview, nothing, just sat down at a desk and started working.  when
managers asked him if he actually wanted paying, he said, "no don't
worry about it".

even the Cortex series was bought from a failed (independent)
VC-backed firm that, due to patents and encryption, couldn't work out
how to get THUMB interoperability.

it's a cluster-poop, completely different from the image of the
"highly successful advanced innovative company" that they are today :)

of course *now* they can offer 7-figure US salaries and incentives to
the India Shakti Team lead developer, but they certainly couldn't have
done that even 10 years ago.

> It will be
> interesting to see how the different initiatives (RISC-V, OpenPower,
> MIPS...) evolve to respond to openness concerns and the need to
> cultivate interest in their offerings more generally.

IBM and NXP/Freescale have to be much more careful.  they are patent
heavy-weights, and you've heard the phrase, "do not annoy the 800lb
gorilla".

IBM takes its responsibility as a world-leader extremely seriously,
and they're providing an extremely sneaky royalty-free patent license
for POWER ISA, which says, "you get free unrestricted use of these
patents as long as you don't ever try to assert a patent - ever -
against us, IBM".

*that's* clever :)

l.


From zapper at disroot.org  Thu Jan  2 01:59:47 2020
From: zapper at disroot.org (zap)
Date: Wed, 1 Jan 2020 20:59:47 -0500
Subject: [Arm-netbook] about Risc-V and Power,
Message-ID: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>

Isn't Risc-V supposedly  supposed to be more secure and isn't open power
based on the old risc? I am just wondering, if the level of evils risc-v
has done, justifies abandoning usage of it when you could just as easily
do some risc-v processors with or without their help and moreover,
power, doesn't it require an immense, even crazy amount of watts?
I guess my point is, they use more battery power than intel even. And
intel is bad enough.

Supposedly though I thought anyone could make risc-v processors as long
as they dont use the trademarks. 

That being said, I noticed you guys have been quiet for a while. I hope
you guys are doing well.  :)

I also hope you can reach your goal, who knows, maybe you can do twice
what you thought someday with even 1W used only while being run.

If  I am misunderstanding something, feel free to let me know, I just
think making a line of Risc-V based processor is the way. Libre of
course, but yeah... and yes I saw your update. 


From lkcl at lkcl.net  Thu Jan  2 04:07:51 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Thu, 2 Jan 2020 04:07:51 +0000
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
Message-ID: <CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>

On 1/2/20, zap <zapper at disroot.org> wrote:
> Isn't Risc-V supposedly  supposed to be more secure and isn't open power
> based on the old risc? I am just wondering, if the level of evils risc-v
> has done, justifies abandoning usage of it when you could just as easily
> do some risc-v processors with or without their help

that's the point: we *can't* do a massive libre / open innovative
enhancement to the RV ISA without official support.

the consequences - the risk of a clash in the ISA - would be
absolutely disastrous.


> I guess my point is, they use more battery power than intel even.

what, PowerPC?  that's a poor micro-architectural choice that doesn't
have anything specifically to do with the ISA, especially when the VLE
book (Variable Length Encoding) exists (equivalent to RVC).

l.


From zapper at disroot.org  Thu Jan  2 04:15:49 2020
From: zapper at disroot.org (zap)
Date: Wed, 1 Jan 2020 23:15:49 -0500
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
Message-ID: <8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>



On 01/01/2020 11:07 PM, Luke Kenneth Casson Leighton wrote:
> On 1/2/20, zap <zapper at disroot.org> wrote:
>> Isn't Risc-V supposedly  supposed to be more secure and isn't open power
>> based on the old risc? I am just wondering, if the level of evils risc-v
>> has done, justifies abandoning usage of it when you could just as easily
>> do some risc-v processors with or without their help
> that's the point: we *can't* do a massive libre / open innovative
> enhancement to the RV ISA without official support.
>
> the consequences - the risk of a clash in the ISA - would be
> absolutely disastrous.
Oh really? That's odd... hmm... so you have to abandon risc-v you are
saying?
Pity that's your only option. I wonder if I should tell others about this.
>
>
>> I guess my point is, they use more battery power than intel even.
> what, PowerPC?  that's a poor micro-architectural choice that doesn't
> have anything specifically to do with the ISA, especially when the VLE
> book (Variable Length Encoding) exists (equivalent to RVC).
>
> l.
Okay, well you did say openpower, what is that?
> _______________________________________________
> arm-netbook mailing list arm-netbook at lists.phcomp.co.uk
> http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook
> Send large attachments to arm-netbook at files.phcomp.co.uk



From cand at gmx.com  Thu Jan  2 08:03:51 2020
From: cand at gmx.com (Lauri Kasanen)
Date: Thu, 2 Jan 2020 10:03:51 +0200
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
Message-ID: <20200102100351.ac6dde7de614f6e749f250a7@gmx.com>

On Wed, 1 Jan 2020 20:59:47 -0500
zap <zapper at disroot.org> wrote:

> Isn't Risc-V supposedly  supposed to be more secure and isn't open power
> based on the old risc? I am just wondering, if the level of evils risc-v
> has done, justifies abandoning usage of it when you could just as easily
> do some risc-v processors with or without their help

The ISA has nothing to do with security. All the meltdown/spectre stuff
is implementation, hence why AMD is unaffected by much of it.

> and moreover,
> power, doesn't it require an immense, even crazy amount of watts?
> I guess my point is, they use more battery power than intel even. And
> intel is bad enough.

The old Mac laptops basically tried to use a desktop cpu on mobile,
kinda what Intel P4 did. It's about design choices, not the
instructions. There are a number of lower-wattage Power cpus; using
that does not mean the chip will burn lots.

The POWER9 chips IBM offers, 90W for 4-core, 160W for 8-core and 190W
for more, they are server chips. Compare to Epycs and Xeons, not to
mobile 15W ones. The older Power core in the Wii U uses around 20W. All
about choices.

> Okay, well you did say openpower, what is that?

IBM released the ISA under open terms, and started the OpenPower
foundation to govern it.

> Oh really? That's odd... hmm... so you have to abandon risc-v you are
> saying? Pity that's your only option. I wonder if I should tell others
> about this.

Just making sure it's clear, the ISA choice is about licensing and
extensibility. Risc-v, mips, power are about equal in other ways; in
some ways, power and mips are better, like existing compiler support.
IOW dropping risc-v is not a loss in ways most users would care about.

- Lauri


From lkcl at lkcl.net  Thu Jan  2 08:11:40 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Thu, 2 Jan 2020 16:11:40 +0800
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
Message-ID: <CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>

On Thursday, January 2, 2020, zap <zapper at disroot.org> wrote:

> .
> >
> > the consequences - the risk of a clash in the ISA - would be
> > absolutely disastrous.
> Oh really? That's odd... hmm... so you have to abandon risc-v you are
> saying?


abandon *innovating* with RISCV, yes.


> Pity that's your only option. I wonder if I should tell others about this.


the circumstances are pretty unique, so it's up to you.  they are:

* a Mass Volume commercial product
* a Mass Volume LIBRE product
* a Mass Volume Libre product where the business opportunity is FULL
TRANSPARENCY
* a paramount need to innovate BEYOND that which is dictated in a fascist
manner by the RISCV Foundation (i.e. they refused to follow Trademark Law's
requirements)


very few other products have  these requirements.

* a closed secretive company that is developing a proprietary extension may
do so as a CUSTOM extension. there is no chance of the extension becoming
public.

* an "open source" product simply implenenting EXISTING standards without
ISA innovation clearly has no problem.

* an "extension vendor" has no problem because they will be selling to
proprietary secretive corporations.

* an academic product also has no problem.

* a NONCOMMERCIAL "open" design which NEVER becomes a commercial product
also gaw no problem.

* an UNSUCCESSFUL or niche product, even if it violates Trademark Law by
using Custom OPcodes without authotisation, that is not intended to be mass
volume also does not cause absolute chaos.


>
> >
> >> I guess my point is, they use more battery power than intel even.
> > what, PowerPC?  that's a poor micro-architectural choice that doesn't
> > have anything specifically to do with the ISA, especially when the VLE
> > book (Variable Length Encoding) exists (equivalent to RVC).
> >
> > l.
> Okay, well you did say openpower, what is that?


google "open power foundation"

l.



-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

From hendrik at topoi.pooq.com  Thu Jan  2 14:53:05 2020
From: hendrik at topoi.pooq.com (Hendrik Boom)
Date: Thu, 2 Jan 2020 09:53:05 -0500
Subject: [Arm-netbook] Libre RISC-V -- I mean OpenPower M-Class GPU
	update
In-Reply-To: <CAPweEDzvQjjUUxXZ7WQziTGfT9OpqiEDRQQH8uZeC5DjpO-TZg@mail.gmail.com>
References: <20191231140447.243978ef@Phenom-II-x6.niklas.com>
	<CAPweEDyf=o9EM=aN+rPmBGWBU8WZEB4av1BX_+MGCs41trUCoA@mail.gmail.com>
	<20191231163027.2304f5d0@Phenom-II-x6.niklas.com>
	<CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
	<20200101153733.76086995@Phenom-II-x6.niklas.com>
	<CAPweEDyoATG_-6ugXZk66Cb4C5DaCx7wqOHeSghjerCFom-ubQ@mail.gmail.com>
	<21d7632c1602a2e880c2c681acd9b07e@boddie.org.uk>
	<CAPweEDzvQjjUUxXZ7WQziTGfT9OpqiEDRQQH8uZeC5DjpO-TZg@mail.gmail.com>
Message-ID: <20200102145305.wpf7bm5jqfoad7ti@topoi.pooq.com>

On Thu, Jan 02, 2020 at 12:28:03AM +0000, Luke Kenneth Casson Leighton wrote:
> 
> IBM takes its responsibility as a world-leader extremely seriously,
> and they're providing an extremely sneaky royalty-free patent license
> for POWER ISA, which says, "you get free unrestricted use of these
> patents as long as you don't ever try to assert a patent - ever -
> against us, IBM".
> 
> *that's* clever :)

Aren't there similar terms in the GPL3?
Except of course you get to use the software instead of any patents?

-- hendrik


From lkcl at lkcl.net  Thu Jan  2 16:13:16 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Fri, 3 Jan 2020 00:13:16 +0800
Subject: [Arm-netbook] Libre RISC-V -- I mean OpenPower M-Class GPU
	update
In-Reply-To: <20200102145305.wpf7bm5jqfoad7ti@topoi.pooq.com>
References: <20191231140447.243978ef@Phenom-II-x6.niklas.com>
	<CAPweEDyf=o9EM=aN+rPmBGWBU8WZEB4av1BX_+MGCs41trUCoA@mail.gmail.com>
	<20191231163027.2304f5d0@Phenom-II-x6.niklas.com>
	<CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
	<20200101153733.76086995@Phenom-II-x6.niklas.com>
	<CAPweEDyoATG_-6ugXZk66Cb4C5DaCx7wqOHeSghjerCFom-ubQ@mail.gmail.com>
	<21d7632c1602a2e880c2c681acd9b07e@boddie.org.uk>
	<CAPweEDzvQjjUUxXZ7WQziTGfT9OpqiEDRQQH8uZeC5DjpO-TZg@mail.gmail.com>
	<20200102145305.wpf7bm5jqfoad7ti@topoi.pooq.com>
Message-ID: <CAPweEDy1OR04dNxcwUdFMC-nczFVxQfs1uNUp=R9NKFewCBPUA@mail.gmail.com>

On Thursday, January 2, 2020, Hendrik Boom <hendrik at topoi.pooq.com> wrote:

> On Thu, Jan 02, 2020 at 12:28:03AM +0000, Luke Kenneth Casson Leighton
> wrote:
> >
> > IBM takes its responsibility as a world-leader extremely seriously,
> > and they're providing an extremely sneaky royalty-free patent license
> > for POWER ISA, which says, "you get free unrestricted use of these
> > patents as long as you don't ever try to assert a patent - ever -
> > against us, IBM".
> >
> > *that's* clever :)
>
> Aren't there similar terms in the GPL3?
> Except of course you get to use the software instead of any patents?


i believe so.  section 8 specifically mentions termination including patent
grants.

however section 11 itself is dreadfully unclear.

l.




-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

From doark at mail.com  Fri Jan  3 17:54:14 2020
From: doark at mail.com (David Niklas)
Date: Fri, 3 Jan 2020 12:54:14 -0500
Subject: [Arm-netbook] Libre RISC-V -- I mean OpenPower M-Class GPU
 update
In-Reply-To: <CAPweEDy1OR04dNxcwUdFMC-nczFVxQfs1uNUp=R9NKFewCBPUA@mail.gmail.com>
References: <20191231140447.243978ef@Phenom-II-x6.niklas.com>
	<CAPweEDyf=o9EM=aN+rPmBGWBU8WZEB4av1BX_+MGCs41trUCoA@mail.gmail.com>
	<20191231163027.2304f5d0@Phenom-II-x6.niklas.com>
	<CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
	<20200101153733.76086995@Phenom-II-x6.niklas.com>
	<CAPweEDyoATG_-6ugXZk66Cb4C5DaCx7wqOHeSghjerCFom-ubQ@mail.gmail.com>
	<21d7632c1602a2e880c2c681acd9b07e@boddie.org.uk>
	<CAPweEDzvQjjUUxXZ7WQziTGfT9OpqiEDRQQH8uZeC5DjpO-TZg@mail.gmail.com>
	<20200102145305.wpf7bm5jqfoad7ti@topoi.pooq.com>
	<CAPweEDy1OR04dNxcwUdFMC-nczFVxQfs1uNUp=R9NKFewCBPUA@mail.gmail.com>
Message-ID: <20200103125414.7a90f3f2@Phenom-II-x6.niklas.com>

On Fri, 3 Jan 2020 00:13:16 +0800
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> On Thursday, January 2, 2020, Hendrik Boom <hendrik at topoi.pooq.com>
> wrote:
>
> > On Thu, Jan 02, 2020 at 12:28:03AM +0000, Luke Kenneth Casson Leighton
> > wrote:
> > >
> > > IBM takes its responsibility as a world-leader extremely seriously,
> > > and they're providing an extremely sneaky royalty-free patent
> > > license for POWER ISA, which says, "you get free unrestricted use
> > > of these patents as long as you don't ever try to assert a patent -
> > > ever - against us, IBM".
> > >
> > > *that's* clever :)
> >
> > Aren't there similar terms in the GPL3?
> > Except of course you get to use the software instead of any patents?
>
>
> i believe so.  section 8 specifically mentions termination including
> patent grants.
>
> however section 11 itself is dreadfully unclear.
>
> l.
>

IANAL, but when I read the GPL3 I thought it was only patents relating
to the SW in question whereas the POWER ISA agreement was more along the
lines of "no suing for infringement ever".
As in, when you DL the GPL3 SW you can check if it infringes, if yes then
sue, if no then you can use it and be bound to the GPL3. If they change
the SW so that it infringes then you can sue (if you aren't using the
new version).

Sincerely,
David


From paul at boddie.org.uk  Fri Jan  3 21:32:43 2020
From: paul at boddie.org.uk (Paul Boddie)
Date: Fri, 03 Jan 2020 21:32:43 +0000
Subject: [Arm-netbook] Libre RISC-V -- I mean OpenPower M-Class GPU
	update
In-Reply-To: <CAPweEDzvQjjUUxXZ7WQziTGfT9OpqiEDRQQH8uZeC5DjpO-TZg@mail.gmail.com>
References: <20191231140447.243978ef@Phenom-II-x6.niklas.com>
	<CAPweEDyf=o9EM=aN+rPmBGWBU8WZEB4av1BX_+MGCs41trUCoA@mail.gmail.com>
	<20191231163027.2304f5d0@Phenom-II-x6.niklas.com>
	<CAPweEDzHJa_nPePu8AkUQX=Wp-Jh4CB6PJTDi-H-qo14rePcNQ@mail.gmail.com>
	<20200101153733.76086995@Phenom-II-x6.niklas.com>
	<CAPweEDyoATG_-6ugXZk66Cb4C5DaCx7wqOHeSghjerCFom-ubQ@mail.gmail.com>
	<21d7632c1602a2e880c2c681acd9b07e@boddie.org.uk>
	<CAPweEDzvQjjUUxXZ7WQziTGfT9OpqiEDRQQH8uZeC5DjpO-TZg@mail.gmail.com>
Message-ID: <ccb71d32a2e7e961d29e13186f40126b@boddie.org.uk>

On 2020-01-02 00:28, Luke Kenneth Casson Leighton wrote:
> 
> after they got the ARM7 functional, barry managed to get ARM their
> very first license, ever: with Plessey.  they were so happy, they
> offered him a job.  barry turned it down: he would have been employee
> number 12, and a very rich man, now :)

The Plessey connection is interesting to hear about. Of course, Plessey 
got merged into GEC which became GEC Marconi. Ultimately, Marconi, with 
the GEC assets stripped away and with the company focusing on the 
apparently successful telecoms equipment model that made Ericsson a lot 
of money, itself failed.

> but ARM - aka ACORN RISC machines (not Advanced RISC Machines) -
> basically had zero cash, and at one point was completely unable to pay
> its employees (this is like... early 1990s).  they licensed the ARM11
> design to Intel for GBP 100,000, unrestricted, royalty-free, in
> exchange for a promise from the team that IBM had bought (the DEC
> Alpha developers), would "fix all the problems and give the changes
> back".

The story I have heard is that a DEC team did the StrongARM on their own 
initiative - not a surprising thing within DEC if you read about the 
different RISC initiatives within DEC in the 1980s and 1990s and all the 
corporate politics - doing so maybe without a licence and without ARM 
even knowing about it, and then they approached ARM afterwards. Whether 
that story is true or not, it effectively saved ARM's bacon. It 
certainly kept Acorn viable for another couple of years because their 
roadmap was running out of road, waiting for ARM800 or ARM810 CPUs 
which, in their envisaged form, probably never appeared. Also, the 
target frequency would have been modest compared to StrongARM, but that 
probably just shows what expertise DEC had accrued and applied when 
developing Alpha.

Probably the other understated development at that point in ARM's 
history was the introduction of the Cirrus Logic ARM7500 and ARM7500FE 
products which were the first ARM SoCs (as far as I am aware). A bunch 
of network computers and set-top boxes used those products, and they 
also kept Acorn going for some more time. The ARM7500FE also had 
hardware floating point arithmetic, unlike the StrongARM, and it was 
therefore still an attractive choice despite being clocked a lot slower 
than the StrongARM.

> the DEC Alpha developers - whom Intel themselves didn't know what to
> do with, so gave them the PXA Project to do - took one look at the HDL
> and went "holy f*** this is s**t" and started again from scratch.
> they could do so because they had that GBP 100,000 royalty-free
> license from ARM, and the contract wasn't worded carefully enough.
> 
> thus, the PXA 2xx series became the world's first superscalar
> ARM-compatible architecture... *not* the ARM Cortex A8 as ARM keeps
> telling everybody :)

As far as I know the XScale and PXA product lines descend from StrongARM 
as a consequence of the bizarre and rather suspicious settlement between 
DEC and Intel where DEC supposedly won but ended up weakening its own 
position, probably hastening its acquisition by Compaq and the effective 
demise of various technologies like Alpha.

Paul


From zapper at disroot.org  Fri Jan  3 22:57:12 2020
From: zapper at disroot.org (zap)
Date: Fri, 3 Jan 2020 17:57:12 -0500
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
	<CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
Message-ID: <07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>

Just to be clear, you cannot legally sell risc-v processors even if you
remove the trademarks. 

And, OpenPower can be made more secure and lightweight then Risc-V.

Do I have that right?

If so, then I will recommend the Hyperbola devs work within the
OpenPower thought process for making libre, lightweight processors.




From lkcl at lkcl.net  Sat Jan  4 00:25:18 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Sat, 4 Jan 2020 00:25:18 +0000
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
	<CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
	<07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>
Message-ID: <CAPweEDwhiFnO92GiwuT4TuzGwQcNm37AT7D7MVCsuPJ7nQ+Q=A@mail.gmail.com>

On 1/3/20, zap <zapper at disroot.org> wrote:
> Just to be clear, you cannot legally sell risc-v processors even if you
> remove the trademarks.

like any trademark, if you make no mention of the trademark, or any
claims of "compliance", you're probably ok.

from the time i worked on samba-tng, you can claim *compatibility*
with something that is a pun or the *inversion* of a trademark.
"arcfour-compatible" rather than "RC4 compliant".

etnaviv.

v-sirc.

if you say "v-sirc compatible" and you're ok.

> And, OpenPower can be made more secure and lightweight then Risc-V.

that's very difficult to say.  you start having to delve into what
"secure" means at both the architectural, ISA *and* design level.
"lightweight" is much easier to compare however would still take a
significant amount of time.

> Do I have that right?
>
> If so, then I will recommend the Hyperbola devs work within the
> OpenPower thought process for making libre, lightweight processors.
>
>
>
> _______________________________________________
> arm-netbook mailing list arm-netbook at lists.phcomp.co.uk
> http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook
> Send large attachments to arm-netbook at files.phcomp.co.uk


From zapper at disroot.org  Sat Jan  4 01:25:42 2020
From: zapper at disroot.org (zap)
Date: Fri, 3 Jan 2020 20:25:42 -0500
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <CAPweEDwhiFnO92GiwuT4TuzGwQcNm37AT7D7MVCsuPJ7nQ+Q=A@mail.gmail.com>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
	<CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
	<07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>
	<CAPweEDwhiFnO92GiwuT4TuzGwQcNm37AT7D7MVCsuPJ7nQ+Q=A@mail.gmail.com>
Message-ID: <04d46409-2d02-12c1-cd21-7776c9ec7e64@disroot.org>



On 01/03/2020 07:25 PM, Luke Kenneth Casson Leighton wrote:
> On 1/3/20, zap <zapper at disroot.org> wrote:
>> Just to be clear, you cannot legally sell risc-v processors even if you
>> remove the trademarks.
> like any trademark, if you make no mention of the trademark, or any
> claims of "compliance", you're probably ok.
>
> from the time i worked on samba-tng, you can claim *compatibility*
> with something that is a pun or the *inversion* of a trademark.
> "arcfour-compatible" rather than "RC4 compliant".
>
> etnaviv.
>
> v-sirc.
>
> if you say "v-sirc compatible" and you're ok.
So to be clear, is it because it could be very dangerous to work on
risc-v without their help.
>> And, OpenPower can be made more secure and lightweight then Risc-V.
> that's very difficult to say.  you start having to delve into what
> "secure" means at both the architectural, ISA *and* design level.
> "lightweight" is much easier to compare however would still take a
> significant amount of time.
>
>
Well said then. Lightweight is what I concern over more to be fair. I am
sure they are both equally or close to equally secure though - the
meltdown spectre crap. ;)


From lkcl at lkcl.net  Sat Jan  4 01:34:15 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Sat, 4 Jan 2020 01:34:15 +0000
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <04d46409-2d02-12c1-cd21-7776c9ec7e64@disroot.org>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
	<CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
	<07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>
	<CAPweEDwhiFnO92GiwuT4TuzGwQcNm37AT7D7MVCsuPJ7nQ+Q=A@mail.gmail.com>
	<04d46409-2d02-12c1-cd21-7776c9ec7e64@disroot.org>
Message-ID: <CAPweEDyxq_BxGQcsruQet65n6XVdsERmeXmnHH3Jk7qGB9arsA@mail.gmail.com>

On 1/4/20, zap <zapper at disroot.org> wrote:
>
>
> On 01/03/2020 07:25 PM, Luke Kenneth Casson Leighton wrote:
>> On 1/3/20, zap <zapper at disroot.org> wrote:
>>> Just to be clear, you cannot legally sell risc-v processors even if you
>>> remove the trademarks.
>> like any trademark, if you make no mention of the trademark, or any
>> claims of "compliance", you're probably ok.
>>
>> from the time i worked on samba-tng, you can claim *compatibility*
>> with something that is a pun or the *inversion* of a trademark.
>> "arcfour-compatible" rather than "RC4 compliant".
>>
>> etnaviv.
>>
>> v-sirc.
>>
>> if you say "v-sirc compatible" and you're ok.
> So to be clear, is it because it could be very dangerous to work on
> risc-v without their help.

no, not at all.  there's no need for "help".  and it's not "dangerous", either.

* RISC-V is Trademarked.
* therefore if you want to use the Trademark, you *must* respect the
requirements set by the Trademark Holder.
* if you do not want to use the Trademark in connection with your
product, you do *NOT* have to meet the requirements.

there is no "danger" here, nor a "need for help".

in addition:

* if the Trademark Holder acts in a persistently UNREASONABLE WAY,
they LOSE the Trademark.

>>> And, OpenPower can be made more secure and lightweight then Risc-V.
>> that's very difficult to say.  you start having to delve into what
>> "secure" means at both the architectural, ISA *and* design level.
>> "lightweight" is much easier to compare however would still take a
>> significant amount of time.
>>
>>
> Well said then. Lightweight is what I concern over more to be fair. I am
> sure they are both equally or close to equally secure though - the
> meltdown spectre crap. ;)

that's a micro-architectural design decision, not a fault of the ISA itself.

l.


From zapper at disroot.org  Sat Jan  4 01:39:00 2020
From: zapper at disroot.org (zap)
Date: Fri, 3 Jan 2020 20:39:00 -0500
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <CAPweEDyxq_BxGQcsruQet65n6XVdsERmeXmnHH3Jk7qGB9arsA@mail.gmail.com>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
	<CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
	<07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>
	<CAPweEDwhiFnO92GiwuT4TuzGwQcNm37AT7D7MVCsuPJ7nQ+Q=A@mail.gmail.com>
	<04d46409-2d02-12c1-cd21-7776c9ec7e64@disroot.org>
	<CAPweEDyxq_BxGQcsruQet65n6XVdsERmeXmnHH3Jk7qGB9arsA@mail.gmail.com>
Message-ID: <7431fb07-a993-dccb-b4d8-ecdaca66b9a2@disroot.org>

>>> like any trademark, if you make no mention of the trademark, or any
>>> claims of "compliance", you're probably ok.
>>>
>>> from the time i worked on samba-tng, you can claim *compatibility*
>>> with something that is a pun or the *inversion* of a trademark.
>>> "arcfour-compatible" rather than "RC4 compliant".
>>>
>>> etnaviv.
>>>
>>> v-sirc.
>>>
>>> if you say "v-sirc compatible" and you're ok.
>> So to be clear, is it because it could be very dangerous to work on
>> risc-v without their help.
> no, not at all.  there's no need for "help".  and it's not "dangerous", either.
>
> * RISC-V is Trademarked.
> * therefore if you want to use the Trademark, you *must* respect the
> requirements set by the Trademark Holder.
> * if you do not want to use the Trademark in connection with your
> product, you do *NOT* have to meet the requirements.
>
> there is no "danger" here, nor a "need for help".
>
> in addition:
>
> * if the Trademark Holder acts in a persistently UNREASONABLE WAY,
> they LOSE the Trademark.
>
hmm... okay. I must've gotten confused then. I will wait to see your
plans and whether you plan to make your own risc-v or openpower
processor then.

I wish you the best on this,
>>>> And, OpenPower can be made more secure and lightweight then Risc-V.
>>> that's very difficult to say.  you start having to delve into what
>>> "secure" means at both the architectural, ISA *and* design level.
>>> "lightweight" is much easier to compare however would still take a
>>> significant amount of time.
>>>
>>>
>> Well said then. Lightweight is what I concern over more to be fair. I am
>> sure they are both equally or close to equally secure though - the
>> meltdown spectre crap. ;)
> that's a micro-architectural design decision, not a fault of the ISA itself.

Oh, okay. I wonder how much the softcore's use in watts.


https://openpowerfoundation.org/openpower-summit-north-america-2019-introducing-the-microwatt-fpga-soft-cpu-core/





From lkcl at lkcl.net  Sat Jan  4 01:44:22 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Sat, 4 Jan 2020 01:44:22 +0000
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <7431fb07-a993-dccb-b4d8-ecdaca66b9a2@disroot.org>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
	<CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
	<07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>
	<CAPweEDwhiFnO92GiwuT4TuzGwQcNm37AT7D7MVCsuPJ7nQ+Q=A@mail.gmail.com>
	<04d46409-2d02-12c1-cd21-7776c9ec7e64@disroot.org>
	<CAPweEDyxq_BxGQcsruQet65n6XVdsERmeXmnHH3Jk7qGB9arsA@mail.gmail.com>
	<7431fb07-a993-dccb-b4d8-ecdaca66b9a2@disroot.org>
Message-ID: <CAPweEDzCfisaGuDxzd2kDAiUojVjm-+Y7UbQgDK_vm=YRBZbwA@mail.gmail.com>

On 1/4/20, zap <zapper at disroot.org> wrote:

> hmm... okay. I must've gotten confused then.

yes :)  it's what's *not* done that matters, not what *is* done.

> I will wait to see your
> plans and whether you plan to make your own risc-v or openpower
> processor then.

both.

absolute to-the-letter RV64GC compliance in *userspace*... *ONLY*.
with full POWER compliance in ***BOTH*** userspace  ****AND**** kernelspace.

> Oh, okay. I wonder how much the softcore's use in watts.
>
>
> https://openpowerfoundation.org/openpower-summit-north-america-2019-introducing-the-microwatt-fpga-soft-cpu-core/

a lot, compared to an ASIC - this is to be expected.

l.


From zapper at disroot.org  Sat Jan  4 01:49:03 2020
From: zapper at disroot.org (zap)
Date: Fri, 3 Jan 2020 20:49:03 -0500
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <CAPweEDzCfisaGuDxzd2kDAiUojVjm-+Y7UbQgDK_vm=YRBZbwA@mail.gmail.com>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
	<CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
	<07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>
	<CAPweEDwhiFnO92GiwuT4TuzGwQcNm37AT7D7MVCsuPJ7nQ+Q=A@mail.gmail.com>
	<04d46409-2d02-12c1-cd21-7776c9ec7e64@disroot.org>
	<CAPweEDyxq_BxGQcsruQet65n6XVdsERmeXmnHH3Jk7qGB9arsA@mail.gmail.com>
	<7431fb07-a993-dccb-b4d8-ecdaca66b9a2@disroot.org>
	<CAPweEDzCfisaGuDxzd2kDAiUojVjm-+Y7UbQgDK_vm=YRBZbwA@mail.gmail.com>
Message-ID: <b0929458-5db4-173e-1ab9-f44f7f5c5d98@disroot.org>


>> I will wait to see your
>> plans and whether you plan to make your own risc-v or openpower
>> processor then.
> both.
>
> absolute to-the-letter RV64GC compliance in *userspace*... *ONLY*.
> with full POWER compliance in ***BOTH*** userspace  ****AND**** kernelspace.
Hmm, okay sounds good, thanks for clearing up that mystery. Still I do
love that risc-v is supposedly ultra lightweight. Too bad about their
dracoian methods... ;/ They really are like the mozilla of processors.
>
>> Oh, okay. I wonder how much the softcore's use in watts.
>>
>>
>> https://openpowerfoundation.org/openpower-summit-north-america-2019-introducing-the-microwatt-fpga-soft-cpu-core/
> a lot, compared to an ASIC - this is to be expected.
At least  until the power developers make some ultra lightweight
processors right? Whenever that happens...




From lkcl at lkcl.net  Sat Jan  4 01:52:24 2020
From: lkcl at lkcl.net (Luke Kenneth Casson Leighton)
Date: Sat, 4 Jan 2020 01:52:24 +0000
Subject: [Arm-netbook] about Risc-V and Power,
In-Reply-To: <b0929458-5db4-173e-1ab9-f44f7f5c5d98@disroot.org>
References: <e2e9a66e-8e1f-575b-8a4a-567e9c012376@disroot.org>
	<CAPweEDxiAqqScnD+G_uAyJ4Fnac_6gsme4aQdfMtNaSaKM4f6w@mail.gmail.com>
	<8ba426d9-dce4-b49c-2b08-6c643265c885@disroot.org>
	<CAPweEDxt=hAmL-LOurHqGNLqO57GGgCZS6tT1e2Y3WMcWgdBvw@mail.gmail.com>
	<07cf0d34-212b-f1f8-1c38-b606d534942c@disroot.org>
	<CAPweEDwhiFnO92GiwuT4TuzGwQcNm37AT7D7MVCsuPJ7nQ+Q=A@mail.gmail.com>
	<04d46409-2d02-12c1-cd21-7776c9ec7e64@disroot.org>
	<CAPweEDyxq_BxGQcsruQet65n6XVdsERmeXmnHH3Jk7qGB9arsA@mail.gmail.com>
	<7431fb07-a993-dccb-b4d8-ecdaca66b9a2@disroot.org>
	<CAPweEDzCfisaGuDxzd2kDAiUojVjm-+Y7UbQgDK_vm=YRBZbwA@mail.gmail.com>
	<b0929458-5db4-173e-1ab9-f44f7f5c5d98@disroot.org>
Message-ID: <CAPweEDysH55HEMn6oJDSyRAcb_+f-fGoHeRaD1=Azeed_=XiPQ@mail.gmail.com>

On 1/4/20, zap <zapper at disroot.org> wrote:

> Hmm, okay sounds good, thanks for clearing up that mystery. Still I do
> love that risc-v is supposedly ultra lightweight. Too bad about their
> dracoian methods... ;/

not draconian: just blatantly arrogant.

> They really are like the mozilla of processors.

indeed.

>>
>>> Oh, okay. I wonder how much the softcore's use in watts.
>>>
>>>
>>> https://openpowerfoundation.org/openpower-summit-north-america-2019-introducing-the-microwatt-fpga-soft-cpu-core/
>> a lot, compared to an ASIC - this is to be expected.
> At least  until the power developers make some ultra lightweight
> processors right? Whenever that happens...

FPGAs automatically come with a power consumption penalty compared to
an ASIC, for a given clockrate in both.  therefore, if you drastically
cut the performance and expectations back far enough, such that power
consumption is "acceptable"... then yes.

this does not have anything to do with the ISA (per se).

l.


From paul at boddie.org.uk  Fri Jan 24 15:22:49 2020
From: paul at boddie.org.uk (Paul Boddie)
Date: Fri, 24 Jan 2020 16:22:49 +0100
Subject: [Arm-netbook] EOMA68 Computing Devices Update: Measurements and
	a Hypothesis
In-Reply-To: <CAPweEDzWOHzKT6aUT=YQCE096suL3QdDSbeEnM+CcfEBdu=55g@mail.gmail.com>
References: <2142097.Xevr7QOWls@jeremy>
	<CAPweEDzWOHzKT6aUT=YQCE096suL3QdDSbeEnM+CcfEBdu=55g@mail.gmail.com>
Message-ID: <3931777.0RUxNtIiD3@jeremy>

Hello,

Sorry, just warming this thread up with a few random observations...

On Monday 2. December 2019 20.05.55 Luke Kenneth Casson Leighton wrote:
> On Mon, Dec 2, 2019 at 3:23 PM Paul Boddie <paul at boddie.org.uk> wrote:
> > 
> > https://www.crowdsupply.com/eoma68/micro-desktop/updates/measurements-and-> > a-hypothesis
> > 
> > From what it says, it rather sounds like same (or a similar) problem is
> > being encountered as the one which happened with the Ingenic JZ4775
> > boards:
> yehyeh.  except i didn't know about the PCBs not actually matching the
> gerber files, back then.

OK, that would have been a bit awkward for troubleshooting, too.

[...]

> i did actually partly get them up and running, but i'd put a 24mhz XTAL on
> instead of 48mhz, and the SD/MMC wasn't having it.  i tried fixing that in
> software (doubling the PLL frequencies for the SD/MMC) but couldn't get it
> up and running.

Yes, I imagine that the external oscillator is supposed to be 48MHz, and there 
may well be a limit to how far you can get (and how well it will work) by just 
using the PLL multipliers to get you to the frequencies you want.

> with it only being single-core 1ghz MIPS32 i dropped the investigation.

Interestingly, these SoCs all have other cores tucked away inside them, 
although you probably can't get away with regarding them as "proper" cores. 
For instance, on the JZ4780 (which is dual-core), but also the JZ4770, JZ4760 
and most likely the JZ4775, there's a core called AUX in the VPU and another 
one called MCU in the programmable DMA peripheral, both of them being XBurst 
cores but without certain amenities. Typically, they lack full MMUs, cache, 
FPUs and other things, but they seem to have fast access to some cache-like 
memory (TCSM).

I imagine that with a bit more investigation, other cores will pop up, but it 
is interesting how they get a lot of mileage out of the same architecture 
instead of mixing and matching (like the ARC cores in Intel CPUs or the 
OpenRISC cores in Allwinner SoCs). I was also trying to find out a bit more 
about the dedicated video and "vector matrix arithmetic" blocks associated 
with the VPU functionality, and one has to wonder what is going on there as 
well.

Meanwhile, I wonder if you have heard from Mike lately or whether things are 
generally stalled with regard to the production issues. I guess that there 
will be a few weeks of holiday and disruption to take into account now, but I 
thought that maybe you'd caught up with him before the break.

Anyway, hope things are working out wherever you might be. (And that also goes 
for other readers of the list, of course!)

Paul