[Arm-netbook] OLIMEX A10 board

Tsvetan Usunov - OLIMEX Ltd usunov at olimex.com
Sat May 26 11:52:14 BST 2012

>  the DDR3 RAM circuit, if you do not use PADS, and do not keep those
> DDR3 connections EXACTLY the same, you will be in for a bit of a shock
> when it comes to doing the development of the A10 board.
why? let's not act like chinese factory with copy and paste designs :)

>  wits-tech's PADS layout has done the hard part.  if you deviate from
> that you will need to spend several man-months replicating that costly
> work.
this is what I read on their PDF schematic:

DQ0-7、DQM0、DQS0 Length matching 100mil
DQ8-15、DQM1、DQS1 Length matching 100mil
DQ16-23、DQM2、DQS2 Length matching 100mil
DQ24-31、DQM3、DQS3 Length matching 100mil
DA、CONTROL、CK Length matching 300mil
DQSn、DQSn# Differential pairs Z0= 100 ohm,Length matching 10mil
CK、CK# Differential pairs Z0= 100 ohm,Length matching 10mil

and this is pretty much same as on the other DDR3 requirements I've seen
for other processors like AM335X for instance
seems to me not hard to accomplish simple rules: keep length same and
impedance as required and there should be no issues with proper ground
planes. It would be good to have look at what they did, but I can see it
even on Mele1000 I have as the signal routing is on the top and bottom with
ground planes on the inner layers

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