[Arm-netbook] UBoot for Allwinner F20 (Sun3i) - SD/MMC clocks/registers

sysfwlab sysfwlab at gmail.com
Wed May 23 17:25:16 BST 2012


Le 23/05/2012 08:30, Tom Cubie a écrit :
>
>
> On Wed, May 23, 2012 at 11:26 AM, sysfwlab <sysfwlab at gmail.com 
> <mailto:sysfwlab at gmail.com>> wrote:
>
>     Hello everybody,
>
>     My final goal is to modify uboot-allwinner to support sun3i platform.
>     After successfully building a minimal application ("Dummy Sun3i
>     bootloader") that blink a led and after manage the UART0, i improve it
>     with small clocking, math, printf, dump tools, etc..and i learn a
>     lot of
>     things.
>     (Here is a synthesis in french, but ascii schematics are in english
>     http://www.sysfwlab.com/?cat=8)
>
>     Now, i want to play with SD/MMC driver. I do a A10 source analysis
>     and i
>     got a lot of information but i need help, i got some questions and
>     need
>     your experience...
>
>     You can found here A10 uboot SD/MMC driver analysis synthesis (if
>     need):
>     http://www.sysfwlab.com/?p=564
>
>     You can found here F20 uboot SD/MMC driver adaptation analysis
>     synthesis
>     (if need) :
>     http://www.sysfwlab.com/?p=585
>
>     Here is my questions, hope someone can help me :
>
>     1 - I found the F20 controller base address SDCx_BASE and i know the
>     SD/MMC registers offsets for A10 (gctrl,clkcr,timeout,with,etc...) do
>     you think is reasonable to think the SD/MMC controler is the same
>     on F10
>     and A10 so registers offset can be identicale ?
>
> I can tell you F20 and A10 has the same SD controller. But the CCU is 
> different.
>
>     2 - My main probleme is the main clocks registers.
>     On A10 we got 4 clock registers, one clock register per controller
>     (ex:
>     SDC0_CLK : 0x01c20088 for  SDC0_BASE : 0x01c0f000 )
>     On F20 we got only 2 clock registers, one clock register for two
>     controllers .
>     (ex: SDC01_CLK : 0x01c20018 for SDC0_BASE : 0x01c0f000 and SDC1_BASE :
>     0x01c10000)
>
>     Here is what i known on a clock register  for A10 (it's suffisant to
>     enable it):
>     -------------------------------------------------
>      Register : SDC0_CLK - Base : 0x01c20088
>                      SDC1_CLK              0x01c2008c
>                      SDC2_CLK              0x01c20090
>                      SDC3_CLK              0x01c20094
>     -------------------------------------------------
>      BITS |   DESCRIPTION
>     -------------------------------------------------
>       0      \
>       1       | Divider - 011: 3, 100: 4
>       2      /
>       3
>       4
>      ...
>      23
>      24      1 ???
>      25
>      ...
>      30
>      31      1  ???
>     =================================================
>
>     Did you get and idea ? Do you think the register organisation for
>     F20 is
>     the same expect i manage 2 controllers at once ?
>     (Did you ever see this on other CPU ?)
>
>     3 - Controller frequency
>     I compute uboot start A10 CPU at 504MHz and PLL5 witch drive SD/MMC
>     controllers at 360 MHz, do you think is something common ?
>
>     4 - Linux & Sun3i SD/MMC driver
>     I dont find SD/MMC allwinner reference on linux-allwinner tree, but i
>     know it can read SD, can someone help me to find and entry point ?
>     (I ever read /drivers, /includes, but nothing about allwinner
>     register,
>     etc...it go throught  drivers/platform structures callback and
>     callback
>     and callback...:) and nothing about mmc and low level allwinner
>     acces....please help ) it's a standard component ? (like UART is 16555
>     clone ?)
>
>     5 - More generally if someone can give me the SD/MMC map register for
>     F20 it will be the best but all information, idea and expericence are
>     well come...Please Mr Allwinner, open this registers :), please... 
>
>
>
>     6 - Subsidiar : I got a main clock named "VE_PLL" (in top off the
>     clock
>     hierarchy, near "CORE_PLL", do you now what does "VE" mean ?
>         (Video Engine ? ...it seame to be an important module but....)
>
>     Thanks a lot in advance,
>     (and sorry for expression)
>
>     Bin
>
>
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>
>
>
> -- 
> Keep simple, stay foolish.
>
>
>
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Hello Tom and Everybody,

Ok, i thinks was tired yesterday...with a cleared brain, i found myself. 
For information, and comparaison, here is the A10 SD/MMC contrôler main 
clocks registers :

=================================================
           A10 SD/MMC MAIN CLOCK MODULE
=================================================
  Manage A10 SD/MMC controler main clock
-------------------------------------------------
  Register : SDC0_CLK - Base : 0x01c20088
             SDC1_CLK          0x01c2008c
             SDC2_CLK          0x01c20090
             SDC3_CLK          0x01c20094
-------------------------------------------------
  BITS |   DESCRIPTION
-------------------------------------------------
   0      \
   1       |   clock divide ratio,
   2       |   (divided by (m+1), ex: 1~16)
   3      /
   4      \
   5       |
   6       |
   7       |
   8       |
   9       |   Reserved
  10       |
  11       |
  12       |
  13       |
  14       |
  15      /
  16      \    clock pre-divide ratio,
  17      /    predivided by 2^n , ex: 1/2/4/8
  18      \
  19       |
  20       |
  21       |   Reserved
  22       |
  23      /
  24      \    clock source select,
  25      /    (00: HOSC, 01: PLL6, 10: PLL5, 11: reserved)
  26      \
  27       |
  28       |   Reserverd
  29       |
  30      /
  31      Gating special clock, 0-CLOCK OFF, 1-CLOCK ON
=================================================


Here is F20 SD/MMC controller main clock module

=================================================
    Register : SDC01_CLK - Base :  0x01c20018
               SDC23_CLK           0x01c2001C
=================================================
  Manage SD/MMC controler main clock
-------------------------------------------------
  BITS |   DESCRIPTION
-------------------------------------------------
   0      \
   1       |  SDC0/SDC2 divider
   2       |  (val=divider-1)
   3      /
   4      \  SDC0/SDC2 source select
   5      /  (00: PLL0, 01: forbidden, 10:SDRAM_PLL, 11: CORE_PLL)
   6
   7      1: SDC0/SDC2 enabled, 0: SDC0/SDC2 disabled
   8      \
   9       | SDC1/SDC3 divider
  10       | (val=divider-1)
  11      /
  12      \  SDC1/SDC3 source select
  13      /  (00: PLL0, 01: forbidden, 10:SDRAM_PLL, 11: CORE_PLL)
  14
  15      1: SDC1/SDC3 enabled, 0: SDC1/SDC3 disabled
=================================================

Ok, i think a got all data i need to play with the F20 SD/MMC contrôler...

An other thanks for you help Tom,  i hope i can disturbe you another 
time if i got another problème...

Best regards

Bin

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