[Arm-netbook] UBoot for Allwinner F20 (Sun3i) - SD/MMC clocks/registers

[Tom Cubie]

On Wed, May 23, 2012 at 11:26 AM, sysfwlab <sysfwlab at gmail.com> wrote:

> Hello everybody,
>
> My final goal is to modify uboot-allwinner to support sun3i platform.
> After successfully building a minimal application ("Dummy Sun3i
> bootloader") that blink a led and after manage the UART0, i improve it
> with small clocking, math, printf, dump tools, etc..and i learn a lot of
> things.
> (Here is a synthesis in french, but ascii schematics are in english
> http://www.sysfwlab.com/?cat=8)
>
> Now, i want to play with SD/MMC driver. I do a A10 source analysis and i
> got a lot of information but i need help, i got some questions and need
> your experience...
>
> You can found here A10 uboot SD/MMC driver analysis synthesis (if need):
> http://www.sysfwlab.com/?p=564
>
> You can found here F20 uboot SD/MMC driver adaptation analysis synthesis
> (if need) :
> http://www.sysfwlab.com/?p=585
>
> Here is my questions, hope someone can help me :
>
> 1 - I found the F20 controller base address SDCx_BASE and i know the
> SD/MMC registers offsets for A10 (gctrl,clkcr,timeout,with,etc...) do
> you think is reasonable to think the SD/MMC controler is the same on F10
> and A10 so registers offset can be identicale ?
>
> I can tell you F20 and A10 has the same SD controller. But the CCU is
different.

> 2 - My main probleme is the main clocks registers.
> On A10 we got 4 clock registers, one clock register per controller (ex:
> SDC0_CLK : 0x01c20088 for  SDC0_BASE : 0x01c0f000 )
> On F20 we got only 2 clock registers, one clock register for two
> controllers .
> (ex: SDC01_CLK : 0x01c20018 for SDC0_BASE : 0x01c0f000 and SDC1_BASE :
> 0x01c10000)
>
> Here is what i known on a clock register  for A10 (it's suffisant to
> enable it):
> -------------------------------------------------
>  Register : SDC0_CLK - Base : 0x01c20088
>                  SDC1_CLK              0x01c2008c
>                  SDC2_CLK              0x01c20090
>                  SDC3_CLK              0x01c20094
> -------------------------------------------------
>  BITS |   DESCRIPTION
> -------------------------------------------------
>   0      \
>   1       | Divider - 011: 3, 100: 4
>   2      /
>   3
>   4
>  ...
>  23
>  24      1 ???
>  25
>  ...
>  30
>  31      1  ???
> =================================================
>
> Did you get and idea ? Do you think the register organisation for F20 is
> the same expect i manage 2 controllers at once ?
> (Did you ever see this on other CPU ?)
>
> 3 - Controller frequency
> I compute uboot start A10 CPU at 504MHz and PLL5 witch drive SD/MMC
> controllers at 360 MHz, do you think is something common ?
>
> 4 - Linux & Sun3i SD/MMC driver
> I dont find SD/MMC allwinner reference on linux-allwinner tree, but i
> know it can read SD, can someone help me to find and entry point ?
> (I ever read /drivers, /includes, but nothing about allwinner register,
> etc...it go throught  drivers/platform structures callback and callback
> and callback...:) and nothing about mmc and low level allwinner
> acces....please help ) it's a standard component ? (like UART is 16555
> clone ?)
>
> 5 - More generally if someone can give me the SD/MMC map register for
> F20 it will be the best but all information, idea and expericence are
> well come...Please Mr Allwinner, open this registers :), please...


>
> 6 - Subsidiar : I got a main clock named "VE_PLL" (in top off the clock
> hierarchy, near "CORE_PLL", do you now what does "VE" mean ?
>     (Video Engine ? ...it seame to be an important module but....)
>
> Thanks a lot in advance,
> (and sorry for expression)
>
> Bin
>
>
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-- 
Keep simple, stay foolish.
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